UNEEC builds STX-2, a European RISC-V accelerator that runs sparse FP64 simulation coupled with AI inference on the same silicon — paired with AI tooling that ports your existing code to it automatically.
HPC users pay more and receive less incremental performance every cycle. GPU price and power are climbing while the software porting tax remains a real barrier.
One architectural choice — lean, explicit, deterministic — makes STX-2 both structurally energy-efficient and able to run your existing code without a manual rewrite.
A chiplet design with RISC-V + sparse FP64 + tensor on the same die, built for FLOPs/pJ. With no data caching and no speculation, performance is a deterministic function of the source — not of hidden state burning energy on every run.
An agentic port → optimize → verify pipeline turns legacy C / C++ / Fortran into tuned, numerically-verified STX-2 kernels automatically — leaving the ported source observable and owned by you. The explicitness that taxes human programmers is exactly what empowers the agent.
The reason inefficient hardware keeps winning isn't physics — it's the cost of moving software to anything new. That is the moat and we're dissolving it.
Lean, explicit architectures are the most energy-efficient — and the hardest to write code for. Every new design demanded a manual rewrite costing person-years, so general-purpose, power-hungry hardware won by default. Efficiency was a penalty you paid in engineering time.
AI code generation collapses the porting cost. Once moving a code to new silicon no longer takes years, the software lock-in that protects incumbents stops being a moat — and hardware competes on energy and price.
Every memory-bound, sparse, iterative HPC workload — and the AI inference that increasingly runs alongside it, on the same silicon.
Beachhead: European sovereign HPC. Power-capped EuroHPC sites, national labs and industrial HPC on 2028–2030 refresh cycles. Europe's exascale flagships run on US accelerators today; no sovereign alternative exists.
Expansion: the edge, on the same silicon. The same compute chiplets scale down into passively-cooled edge modules — with no new tape-out.
Spun out of Fraunhofer's Center for High-Performance Computing — a team that builds HPC software, knows the applications deeply, and understands how chip architecture drives real-world performance. Its predecessor, STX-1, taped out in 12nm — the groundwork STX-2 is built on.
Advised by Prof. Dr. Luca Benini (Univ. Bologna) — pioneer of energy-efficient processor architecture · Dominik Ulmer (VP, Cray, until 2019) · Jürgen Brand (CFO, hardware & software).
If you've built compilers, verified RTL, designed network-on-chip, or written runtimes for HPC systems — and you want your work to reach real silicon and real customers — we should talk.